Paper-Conference

CELLA: A 28nm Compute-Memory Co-Optimized Real-Time Digital CIM-based Edge LLM Accelerator with 1.78ms-response in Prefill and 31.32 Token/s in Decoding

Co-Corresponding Author

Z. Wu, Z. He, B. Yang, Y. Wang, S. Wei, Y. Hu, F. Tu, S. Yin

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design

Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie

CoXplorer: Multi-staged Co-exploration Framework for AI Model Compression and Accelerator Design

Co-Corresponding Author

S. Ma, J. Wu, Y. Tan, P. Dong, P. Luo, D. Pang, Y. Liu, X. Liu, L. Liang, K-T. Cheng, F. Tu

CURE-Fuzz: Curiosity-Driven Reinforcement Learning for Agile Hardware Testing

H. Fan, Y. Wang, X. Zhou, S. Li, B. Zhao, Y. Lyu, J. Xu, W. Zhang

ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring

Dimitrios Tsaras, Xing Li, Lei Chen, Zhiyao Xie, Mingxuan Yuan

Enhancing Large-Scale AI Training Efficiency: The C4 Solution for Real-Time Anomaly Detection and Communication Optimization

J. Dong, B. Luo, J. Zhang, P. Zhang, F. Feng, Y. Zhu, A. Liu, Z. Chen, Y. Shi, Y. Xie

ER-DCIM: Error-Resilient Digital CIM with Run-Time MAC-Cell Error Correction

Co-Corresponding Author

Z. He, Y. Wang, Z. Wu, S. Wei, Y. Hu, F. Tu, S. Yin

FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling

Qijun Zhang, Mengming Li, Yao Lu, Zhiyao Xie

FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration

X. Liu, J. Liang, L. Du, Y. Zhang, C. Ma, H. Fan, J. Xu, W. Zhang

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment

Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Zhiyao Xie