HKUST Computer Architecture Group
HKUST Computer Architecture Group
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COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging
G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs
ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning
MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extension
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage
Transferable Pre-Synthesis PPA Estimation for RTL Designs with Data Augmentation Techniques
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