Paper-Conference

VAR-Turbo: Unlocking the Potential of Visual Autoregressive Models through Dual Redundancy
Corresponding Author
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A 28nm 0.22uJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentation
Co-Corresponding Author, The First Hong Kong AI Chip at ISSCC
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A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
AccelStack: A Cost-Driven Analysis of 3D-Stacked LLM Accelerators
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
Assassyn: A Unified Abstraction for Architectural Simulation and Implementation
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AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling