J. Xu

Latest

• VersaQ-3D: A Reconfigurable Accelerator Enabling Feed-Forward and Generalizable 3D Reconstruction via Versatile Quantization
• AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
• CURE-Fuzz: Curiosity-Driven Reinforcement Learning for Agile Hardware Testing
• DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator
• FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration
• HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantization
• NVMePass: A Lightweight, High-performance and Scalable NVMe Virtualization Architecture with I/O Queues Passthrough
• SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices
• UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHE