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W. Zhang

VersaQ-3D: A Reconfigurable Accelerator Enabling Feed-Forward and Generalizable 3D Reconstruction via Versatile Quantization
AccelStack: A Cost-Driven Analysis of 3D-Stacked LLM Accelerators
AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
CURE-Fuzz: Curiosity-Driven Reinforcement Learning for Agile Hardware Testing
DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator
FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration
HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantization
Inductive Effect-Aware Power Distribution Network Modeling and Analysis for Heterogeneous 3D Integrated Circuits
LLaMCAT: Optimizing Large Language Model Inference with Cache Arbitration and Throttling
Scale, Don't Fine-tune: Guiding Multimodal LLMs for Efficient Visual Place Recognition at Test-Time
SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices
TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms
UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHE

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