HKUST Computer Architecture Group
HKUST Computer Architecture Group
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A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis
COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging
G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs
LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power
MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extension
ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework
ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
Profile-Guided Temporal Prefetching
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage
Transferable Pre-Synthesis PPA Estimation for RTL Designs with Data Augmentation Techniques
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