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Jing Wang

A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis
ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning
IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits

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