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S. Yin

[Forthcoming] Symposium on VLSI Technology and Circuits (VLSI) 2026
Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising-similarity for Diffusion Models
ETCIM: Error-Tolerant Digital CIM Processor with Redundancy-Free Hard Error Repair and Run-Time Soft Error Correction
HR-DCIM: High-Reliability Floating-Point Digital CIM Architecture with Unified Low-Cost Iterative Error Correction
MRCIM: A Many-Core Reconfigurable Computing-in-Memory Processor Combining CPU and Tensor Modes for NN Acceleration
CELLA: A 28nm Compute-Memory Co-Optimized Real-Time Digital CIM-based Edge LLM Accelerator with 1.78ms-response in Prefill and 31.32 Token/s in Decoding
CV-CIM: A Hybrid Domain XOR-derived Similarity-aware Computation-in-memory Supporting Cost Volume Construction
ER-DCIM: Error-Resilient Digital CIM with Run-Time MAC-Cell Error Correction
LLM-CIM: A 28nm 126.7 TOPS/W Input-LUT-based Digital CIM Macro with Reconfigurable Matrix Multiplication and Nonlinear Operation Modes for LLMs
Rethinking Control Flow in Spatial Architectures: Insights into Control Flow Plane Design
TensorCIM: Digital Computing-In-Memory Tensor Processor with Multi-Chip-Module-based Architecture for Beyond-NN Acceleration

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