Paper-Conference

[Forthcoming] Symposium on VLSI Technology and Circuits (VLSI) 2026

Co-Corresponding Author

Z. He, Y. Wang, Z. Yue, Z. Wu, Y. Hu, F. Tu, S. Yin

A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding

Highlight Paper

P. Dong, Y. Tan, X. Liu, P. Luo, Y. Liu, D. Pang, S. Ma, X. Huang, S-Y. Liu, D. Zhang, Z. Lu, L. Liang, C-Y. Tsui, F. Tu, L. Zhao, K-T. Cheng

ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning

Yugao Zhu, Zhicheng Guo, Yuchao Wu, Mengming Li, Jing Wang, Zhiyao Xie

COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging

Yao Lu, Zhicheng Guo, Qijun Zhang, Shang Liu, Wenji Fang, Wenkai Li, Zhiyao Xie

D2CIM: A 28nm 53.3 TFLOPS/W Decoding Digital CIM Macro for Efficient FlashMLA-based LLM Inference

Corresponding Author

J. Chen, Z. Xuan, Y. Li, Z. Yan, Z. Li, Y-F. Yung, Y. Deng, X. Huo, C-Y. Tsui, K-T. Cheng, F. Tu

DAPO: Design Structure Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning

Jinming Ge, Linfeng Du, Likith Anaparty, Shangkun Li, Tingyuan Liang, Afzal Ahmad, Vivek Chaturvedi, Sharad Sinha, Zhiyao Xie, Jiang Xu, Wei Zhang

FlashTFHE: A Scalable Architecture for Efficient Multi-bit Fully Homomorphic Encryption

Jiaao Ma, Ceyu Xu, Ning Liang, Lisa Wu Wills

FSGen: Agile Fused and Sparse Accelerator Generator with Accurate Power Model for LLM Applications

Jay Zhe-an Mok, Qijun Zhang, Zhiyao Xie

G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs

Qijun Zhang, Yao Lu, Shang Liu, Mengming Li, Chen Zhang, Dongbo Wang, Zhiyao Xie

HR-DCIM: High-Reliability Floating-Point Digital CIM Architecture with Unified Low-Cost Iterative Error Correction

Co-Corresponding Author

Z. He, Y. Wang, Z. Yue, Z. Wu, H. Han, S. Wei, Y. Hu, F. Tu, S. Yin