Paper-Conference

SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits

Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie

TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms

E. Li, Z. Lin, S. Sinha, W. Zhang

Towards Accurate and Efficient 3D Object Detection for Autonomous Driving: A Mixture of Experts Computing System on Edge

Linshen Liu, Boyan Su, Junyue Jiang, Guanlin Wu, Cong Guo, Ceyu Xu, Hao Frank Yang

Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage

Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie

TRACI: Network Acceleration of Input-Dynamic Communication for Large-Scale Deep Learning Recommendation Model

G. Huang, H. Li, L. Qin, J. Huang, Y. Kang, Y. Ding, Y. Xie

Uni-Render: A Unified Accelerator for Real-Time Rendering Across Diverse Neural Renderers

Chaojian Li, Sixu Li, Linrui Jiang, Jingqun Zhang, Yingyan (Celine) Lin

UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures

T. Xie, Z. Zhu, B. Li, Y. He, C. Li, G. Sun, H. Yang, Y. Xie, Y. Wang

UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHE

Y. Zhang, S. Sinha, J. Xu, W. Zhang