Publications | HKUST Computer Architecture Grouphttps://computer-arch-dev.hkust.edu.hk/publication/PublicationsHugo Blox Builder (https://hugoblox.com)en-usThu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/media/icon_hu_7613a4a452ac7087.pngPublicationshttps://computer-arch-dev.hkust.edu.hk/publication/[Forthcoming] Symposium on VLSI Technology and Circuits (VLSI) 2026https://computer-arch-dev.hkust.edu.hk/publication/vlsi26/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/vlsi26/A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decodinghttps://computer-arch-dev.hkust.edu.hk/publication/isscc26-reram/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isscc26-reram/A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Acceleratorshttps://computer-arch-dev.hkust.edu.hk/publication/arxiv2026-a-full-stack-performance-evaluation-infr/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/arxiv2026-a-full-stack-performance-evaluation-infr/A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysishttps://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/ALOHA: Accelerating Leveled Fully Homomorphic Encryption with Cryptography-Specific Architectureshttps://computer-arch-dev.hkust.edu.hk/publication/acm2026-aloha-accelerating-leveled-fully-homomo/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/acm2026-aloha-accelerating-leveled-fully-homomo/ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioninghttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-compart-community-guided-post-coarsenin/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-compart-community-guided-post-coarsenin/COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaginghttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-cool-a-cooling-aware-point-transformer/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-cool-a-cooling-aware-point-transformer/D2CIM: A 28nm 53.3 TFLOPS/W Decoding Digital CIM Macro for Efficient FlashMLA-based LLM Inferencehttps://computer-arch-dev.hkust.edu.hk/publication/cicc26-d2cim/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/cicc26-d2cim/DAPO: Design Structure Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learninghttps://computer-arch-dev.hkust.edu.hk/publication/date2026-dapo-design-structure-aware-pass-orderi/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/date2026-dapo-design-structure-aware-pass-orderi/Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising-similarity for Diffusion Modelshttps://computer-arch-dev.hkust.edu.hk/publication/jssc26-denim/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/jssc26-denim/ETCIM: Error-Tolerant Digital CIM Processor with Redundancy-Free Hard Error Repair and Run-Time Soft Error Correctionhttps://computer-arch-dev.hkust.edu.hk/publication/jssc26-etcim/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/jssc26-etcim/FlashTFHE: A Scalable Architecture for Efficient Multi-bit Fully Homomorphic Encryptionhttps://computer-arch-dev.hkust.edu.hk/publication/isca2026-flashtfhe-a-scalable-architecture-for-e/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2026-flashtfhe-a-scalable-architecture-for-e/FSGen: Agile Fused and Sparse Accelerator Generator with Accurate Power Model for LLM Applicationshttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-fsgen-agile-fused-and-sparse-accelerato/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-fsgen-agile-fused-and-sparse-accelerato/G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUshttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-g-power-architecture-level-gpu-power-mo/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-g-power-architecture-level-gpu-power-mo/Hardware-Software Co-design for 3D-DRAM-based LLM Serving Acceleratorhttps://computer-arch-dev.hkust.edu.hk/publication/arxiv2026-hardware-software-co-design-for-3d-dram/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/arxiv2026-hardware-software-co-design-for-3d-dram/HR-DCIM: High-Reliability Floating-Point Digital CIM Architecture with Unified Low-Cost Iterative Error Correctionhttps://computer-arch-dev.hkust.edu.hk/publication/hpca26-hrdcim/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/hpca26-hrdcim/ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesseshttps://computer-arch-dev.hkust.edu.hk/publication/isca2026-icp-exploiting-instruction-correlation/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2026-icp-exploiting-instruction-correlation/IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioninghttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-impart-integration-of-memetic-operation/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-impart-integration-of-memetic-operation/LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Powerhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-leap-a-self-supervised-per-cycle-toggle/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-leap-a-self-supervised-per-cycle-toggle/MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extensionhttps://computer-arch-dev.hkust.edu.hk/publication/tcad2026-mfspart-a-generalized-partitioning-fram/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-mfspart-a-generalized-partitioning-fram/MRCIM: A Many-Core Reconfigurable Computing-in-Memory Processor Combining CPU and Tensor Modes for NN Accelerationhttps://computer-arch-dev.hkust.edu.hk/publication/tcas-i26-mrcim/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcas-i26-mrcim/PF-LLM: Large Language Model Hinted Hardware Prefetchinghttps://computer-arch-dev.hkust.edu.hk/publication/asplos2026-pf-llm-large-language-model-hinted-hard/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asplos2026-pf-llm-large-language-model-hinted-hard/ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Frameworkhttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2026-readypower-a-reliable-interpretable-a/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2026-readypower-a-reliable-interpretable-a/Reconfigurable Quantum Instruction Set Computers for High Performance Attainable on Hardwarehttps://computer-arch-dev.hkust.edu.hk/publication/asplos2026-reconfigurable-quantum-instruction-set-c/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asplos2026-reconfigurable-quantum-instruction-set-c/RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revisionhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-benchmt-dynamic-maintenance-of-rtl/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-benchmt-dynamic-maintenance-of-rtl/RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigmhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-sequencer-towards-scalable-rtl-timi/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-sequencer-towards-scalable-rtl-timi/ShortCircuit: AlphaZero-Driven Generative Circuit Designhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-shortcircuit-alphazero-driven-generativ/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-shortcircuit-alphazero-driven-generativ/Tackling MoE Communication Bottleneck with Dynamic In-Switch Computing on Multi-GPUshttps://computer-arch-dev.hkust.edu.hk/publication/isca2026-tackling-moe-communication-bottleneck-wi/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2026-tackling-moe-communication-bottleneck-wi/The Rise of Tensor Codecshttps://computer-arch-dev.hkust.edu.hk/publication/ieee2026-the-rise-of-tensor-codecs/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/ieee2026-the-rise-of-tensor-codecs/VAR-Turbo: Unlocking the Potential of Visual Autoregressive Models through Dual Redundancyhttps://computer-arch-dev.hkust.edu.hk/publication/hpca26-varturbo/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/hpca26-varturbo/VersaQ-3D: A Reconfigurable Accelerator Enabling Feed-Forward and Generalizable 3D Reconstruction via Versatile Quantizationhttps://computer-arch-dev.hkust.edu.hk/publication/arxiv2026-versaq-3d-a-reconfigurable-accelerator/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/arxiv2026-versaq-3d-a-reconfigurable-accelerator/A 28nm 0.22uJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentationhttps://computer-arch-dev.hkust.edu.hk/publication/isscc25-cnntransformer/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isscc25-cnntransformer/A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Taskshttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-a-self-supervised-pre-trained-and-cros/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-a-self-supervised-pre-trained-and-cros/AccelStack: A Cost-Driven Analysis of 3D-Stacked LLM Acceleratorshttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-accelstack-a-cost-driven-analysis-of-3d/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-accelstack-a-cost-driven-analysis-of-3d/An Architecture-Level CPU Modeling Framework for Power and Other Design Qualitieshttps://computer-arch-dev.hkust.edu.hk/publication/tcad2025-an-architecture-level-cpu-modeling-frame/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-an-architecture-level-cpu-modeling-frame/ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Designhttps://computer-arch-dev.hkust.edu.hk/publication/neurip2025-archpower-dataset-for-architecture-leve/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/neurip2025-archpower-dataset-for-architecture-leve/Assassyn: A Unified Abstraction for Architectural Simulation and Implementationhttps://computer-arch-dev.hkust.edu.hk/publication/isca2025-assassyn-a-unified-abstraction-for-arch/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2025-assassyn-a-unified-abstraction-for-arch/AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMshttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-assertllm-generating-hardware-verificat/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-assertllm-generating-hardware-verificat/ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysishttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-atlas-a-self-supervised-and-cross-stage/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-atlas-a-self-supervised-and-cross-stage/AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAshttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-autoclock-automated-clock-management-fo/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-autoclock-automated-clock-management-fo/AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decouplinghttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-autopower-automated-few-shot-architectu/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-autopower-automated-few-shot-architectu/CELLA: A 28nm Compute-Memory Co-Optimized Real-Time Digital CIM-based Edge LLM Accelerator with 1.78ms-response in Prefill and 31.32 Token/s in Decodinghttps://computer-arch-dev.hkust.edu.hk/publication/vlsi25-cella/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/vlsi25-cella/CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Designhttps://computer-arch-dev.hkust.edu.hk/publication/iclr2025-circuitfusion-multimodal-circuit-repres/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iclr2025-circuitfusion-multimodal-circuit-repres/CoXplorer: Multi-staged Co-exploration Framework for AI Model Compression and Accelerator Designhttps://computer-arch-dev.hkust.edu.hk/publication/iccad25-coxplorer/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad25-coxplorer/CURE-Fuzz: Curiosity-Driven Reinforcement Learning for Agile Hardware Testinghttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-cure-fuzz-curiosity-driven-reinforcemen/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-cure-fuzz-curiosity-driven-reinforcemen/CV-CIM: A Hybrid Domain XOR-derived Similarity-aware Computation-in-memory Supporting Cost Volume Constructionhttps://computer-arch-dev.hkust.edu.hk/publication/jssc25-cvcim/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/jssc25-cvcim/DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Acceleratorhttps://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-draco-co-design-for-dsp-efficient-rigid/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-draco-co-design-for-dsp-efficient-rigid/ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoringhttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-elf-efficient-logic-synthesis-by-prunin/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-elf-efficient-logic-synthesis-by-prunin/Enhancing Large-Scale AI Training Efficiency: The C4 Solution for Real-Time Anomaly Detection and Communication Optimizationhttps://computer-arch-dev.hkust.edu.hk/publication/hpca2025-enhancing-large-scale-ai-training-effici/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/hpca2025-enhancing-large-scale-ai-training-effici/ER-DCIM: Error-Resilient Digital CIM with Run-Time MAC-Cell Error Correctionhttps://computer-arch-dev.hkust.edu.hk/publication/hpca25-erdcim/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/hpca25-erdcim/Exploiting the Memory-Compute-Coupling Feature for CIM Accelerator Design Optimizationhttps://computer-arch-dev.hkust.edu.hk/publication/tcad25-mcc/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad25-mcc/FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modelinghttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-firepower-towards-a-foundation-with-gen/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-firepower-towards-a-foundation-with-gen/FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Accelerationhttps://computer-arch-dev.hkust.edu.hk/publication/icpp2025-flex-leveraging-fpga-cpu-synergy-for-mi/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/icpp2025-flex-leveraging-fpga-cpu-synergy-for-mi/GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmenthttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-geneda-towards-generative-netlist-funct/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-geneda-towards-generative-netlist-funct/H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inferencehttps://computer-arch-dev.hkust.edu.hk/publication/isca2025-h2-llm-hardware-dataflow-co-exploration/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2025-h2-llm-hardware-dataflow-co-exploration/HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantizationhttps://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-hero-hardware-efficient-rl-based-optimi/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-hero-hardware-efficient-rl-based-optimi/HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutionshttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-hlsdebugger-identification-and-correcti/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-hlsdebugger-identification-and-correcti/Inductive Effect-Aware Power Distribution Network Modeling and Analysis for Heterogeneous 3D Integrated Circuitshttps://computer-arch-dev.hkust.edu.hk/publication/isvlsi2025-inductive-effect-aware-power-distributio/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isvlsi2025-inductive-effect-aware-power-distributio/Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiencyhttps://computer-arch-dev.hkust.edu.hk/publication/hpca2025-integrating-prefetcher-selection-with-dy/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/hpca2025-integrating-prefetcher-selection-with-dy/LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localizationhttps://computer-arch-dev.hkust.edu.hk/publication/todaes2025-lithoexp-explainable-two-stage-cnn-base/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/todaes2025-lithoexp-explainable-two-stage-cnn-base/LLaMCAT: Optimizing Large Language Model Inference with Cache Arbitration and Throttlinghttps://computer-arch-dev.hkust.edu.hk/publication/icpp2025-llamcat-optimizing-large-language-model/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/icpp2025-llamcat-optimizing-large-language-model/LLM-CIM: A 28nm 126.7 TOPS/W Input-LUT-based Digital CIM Macro with Reconfigurable Matrix Multiplication and Nonlinear Operation Modes for LLMshttps://computer-arch-dev.hkust.edu.hk/publication/vlsi25-llmcim/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/vlsi25-llmcim/LLM.265: Video Codecs are Secretly Tensor Codecshttps://computer-arch-dev.hkust.edu.hk/publication/micro2025-llm-265-video-codecs-are-secretly-tenso/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/micro2025-llm-265-video-codecs-are-secretly-tenso/Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Acceleratorhttps://computer-arch-dev.hkust.edu.hk/publication/acm2025-matrix-multi-cipher-structures-dataflow/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/acm2025-matrix-multi-cipher-structures-dataflow/Memtunnel: A CXL-based Rack-Scale Host Memory Pooling Architecture for Cloud Servicehttps://computer-arch-dev.hkust.edu.hk/publication/ieee2025-memtunnel-a-cxl-based-rack-scale-host-m/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/ieee2025-memtunnel-a-cxl-based-rack-scale-host-m/NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphhttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-nettag-a-multimodal-rtl-and-layout-alig/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-nettag-a-multimodal-rtl-and-layout-alig/NVMePass: A Lightweight, High-performance and Scalable NVMe Virtualization Architecture with I/O Queues Passthroughhttps://computer-arch-dev.hkust.edu.hk/publication/hpca2025-nvmepass-a-lightweight-high-performanc/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/hpca2025-nvmepass-a-lightweight-high-performanc/Phoenix: Pauli-based High-level Optimization Engine for Instruction Execution on NISQ deviceshttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-phoenix-pauli-based-high-level-optimiza/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-phoenix-pauli-based-high-level-optimiza/PipeDCIM: 28nm 115.11 TOPS/mm2xTOPS/W@1.24GHz Pipeline Digital CIM Macro with an Auto-Design Tool for Diverse High-Performance AI Scenarioshttps://computer-arch-dev.hkust.edu.hk/publication/esserc25-pipedcim/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/esserc25-pipedcim/Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizationshttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-pointer-an-energy-efficient-reram-based/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-pointer-an-energy-efficient-reram-based/PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detectionhttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-pricing-privacy-preserving-circuit-data/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-pricing-privacy-preserving-circuit-data/Profile-Guided Temporal Prefetchinghttps://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/Push Multicast: A Speculative and Coherent Interconnect for Mitigating Manycore CPU Communication Bottleneckhttps://computer-arch-dev.hkust.edu.hk/publication/hpca2025-push-multicast-a-speculative-and-cohere/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/hpca2025-push-multicast-a-speculative-and-cohere/Qubit Mapping and Routing tailored to Advanced Quantum ISAs: Not as Costly as You Thinkhttps://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-qubit-mapping-and-routing-tailored-to-ad/Wed, 01 Jan 2025 00:00:00 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