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Few-Shot Architecture-Level Power Modeling by Power Group Decouplinghttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-autopower-automated-few-shot-architectu/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-autopower-automated-few-shot-architectu/FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modelinghttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-firepower-towards-a-foundation-with-gen/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-firepower-towards-a-foundation-with-gen/GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmenthttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-geneda-towards-generative-netlist-funct/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-geneda-towards-generative-netlist-funct/HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutionshttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-hlsdebugger-identification-and-correcti/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-hlsdebugger-identification-and-correcti/NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graphhttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-nettag-a-multimodal-rtl-and-layout-alig/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-nettag-a-multimodal-rtl-and-layout-alig/Profile-Guided Temporal Prefetchinghttps://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Techniquehttps://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Modelshttps://computer-arch-dev.hkust.edu.hk/publication/emnlp2025-sync-llm-generation-of-large-scale-synt/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/emnlp2025-sync-llm-generation-of-large-scale-synt/Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stagehttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-towards-big-data-in-ai-for-eda-research/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-towards-big-data-in-ai-for-eda-research/Transferable Pre-Synthesis PPA Estimation for RTL Designs with Data Augmentation Techniqueshttps://computer-arch-dev.hkust.edu.hk/publication/tcad2025-transferable-pre-synthesis-ppa-estimatio/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-transferable-pre-synthesis-ppa-estimatio/