<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>X. Liu | HKUST Computer Architecture Group</title><link>https://computer-arch-dev.hkust.edu.hk/author/x.-liu/</link><atom:link href="https://computer-arch-dev.hkust.edu.hk/author/x.-liu/index.xml" rel="self" type="application/rss+xml"/><description>X. Liu</description><generator>Hugo Blox Builder (https://hugoblox.com)</generator><language>en-us</language><lastBuildDate>Thu, 01 Jan 2026 00:00:00 +0000</lastBuildDate><image><url>https://computer-arch-dev.hkust.edu.hk/media/icon_hu_7613a4a452ac7087.png</url><title>X. Liu</title><link>https://computer-arch-dev.hkust.edu.hk/author/x.-liu/</link></image><item><title>A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding</title><link>https://computer-arch-dev.hkust.edu.hk/publication/isscc26-reram/</link><pubDate>Thu, 01 Jan 2026 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/isscc26-reram/</guid><description/></item><item><title>VersaQ-3D: A Reconfigurable Accelerator Enabling Feed-Forward and Generalizable 3D Reconstruction via Versatile Quantization</title><link>https://computer-arch-dev.hkust.edu.hk/publication/arxiv2026-versaq-3d-a-reconfigurable-accelerator/</link><pubDate>Thu, 01 Jan 2026 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/arxiv2026-versaq-3d-a-reconfigurable-accelerator/</guid><description/></item><item><title>A 28nm 0.22uJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentation</title><link>https://computer-arch-dev.hkust.edu.hk/publication/isscc25-cnntransformer/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/isscc25-cnntransformer/</guid><description/></item><item><title>CoXplorer: Multi-staged Co-exploration Framework for AI Model Compression and Accelerator Design</title><link>https://computer-arch-dev.hkust.edu.hk/publication/iccad25-coxplorer/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/iccad25-coxplorer/</guid><description/></item><item><title>DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator</title><link>https://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-draco-co-design-for-dsp-efficient-rigid/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-draco-co-design-for-dsp-efficient-rigid/</guid><description/></item><item><title>FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration</title><link>https://computer-arch-dev.hkust.edu.hk/publication/icpp2025-flex-leveraging-fpga-cpu-synergy-for-mi/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/icpp2025-flex-leveraging-fpga-cpu-synergy-for-mi/</guid><description/></item></channel></rss>