W. Zhang | HKUST Computer Architecture Grouphttps://computer-arch-dev.hkust.edu.hk/author/w.-zhang/W. ZhangHugo Blox Builder (https://hugoblox.com)en-usThu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/media/icon_hu_7613a4a452ac7087.pngW. Zhanghttps://computer-arch-dev.hkust.edu.hk/author/w.-zhang/VersaQ-3D: A Reconfigurable Accelerator Enabling Feed-Forward and Generalizable 3D Reconstruction via Versatile Quantizationhttps://computer-arch-dev.hkust.edu.hk/publication/arxiv2026-versaq-3d-a-reconfigurable-accelerator/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/arxiv2026-versaq-3d-a-reconfigurable-accelerator/AccelStack: A Cost-Driven Analysis of 3D-Stacked LLM Acceleratorshttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-accelstack-a-cost-driven-analysis-of-3d/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-accelstack-a-cost-driven-analysis-of-3d/AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAshttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-autoclock-automated-clock-management-fo/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-autoclock-automated-clock-management-fo/CURE-Fuzz: Curiosity-Driven Reinforcement Learning for Agile Hardware Testinghttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-cure-fuzz-curiosity-driven-reinforcemen/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-cure-fuzz-curiosity-driven-reinforcemen/DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Acceleratorhttps://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-draco-co-design-for-dsp-efficient-rigid/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-draco-co-design-for-dsp-efficient-rigid/FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Accelerationhttps://computer-arch-dev.hkust.edu.hk/publication/icpp2025-flex-leveraging-fpga-cpu-synergy-for-mi/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/icpp2025-flex-leveraging-fpga-cpu-synergy-for-mi/HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantizationhttps://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-hero-hardware-efficient-rl-based-optimi/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-hero-hardware-efficient-rl-based-optimi/Inductive Effect-Aware Power Distribution Network Modeling and Analysis for Heterogeneous 3D Integrated Circuitshttps://computer-arch-dev.hkust.edu.hk/publication/isvlsi2025-inductive-effect-aware-power-distributio/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isvlsi2025-inductive-effect-aware-power-distributio/LLaMCAT: Optimizing Large Language Model Inference with Cache Arbitration and Throttlinghttps://computer-arch-dev.hkust.edu.hk/publication/icpp2025-llamcat-optimizing-large-language-model/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/icpp2025-llamcat-optimizing-large-language-model/Scale, Don't Fine-tune: Guiding Multimodal LLMs for Efficient Visual Place Recognition at Test-Timehttps://computer-arch-dev.hkust.edu.hk/publication/ifac-p2025-scale-don-t-fine-tune-guiding-multimod/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/ifac-p2025-scale-don-t-fine-tune-guiding-multimod/SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Deviceshttps://computer-arch-dev.hkust.edu.hk/publication/date2025-spnerf-memory-efficient-sparse-volumetr/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/date2025-spnerf-memory-efficient-sparse-volumetr/TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platformshttps://computer-arch-dev.hkust.edu.hk/publication/fpga2025-tapca-an-interface-aware-cache-manageme/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/fpga2025-tapca-an-interface-aware-cache-manageme/UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHEhttps://computer-arch-dev.hkust.edu.hk/publication/date2025-unit-a-highly-unified-and-memory-effici/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/date2025-unit-a-highly-unified-and-memory-effici/