Mengming Li | HKUST Computer Architecture Grouphttps://computer-arch-dev.hkust.edu.hk/author/mengming-li/Mengming LiHugo Blox Builder (https://hugoblox.com)en-usThu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/media/icon_hu_7613a4a452ac7087.pngMengming Lihttps://computer-arch-dev.hkust.edu.hk/author/mengming-li/A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysishttps://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioninghttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-compart-community-guided-post-coarsenin/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-compart-community-guided-post-coarsenin/G-Power: Architecture-level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUshttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-g-power-architecture-level-gpu-power-mo/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-g-power-architecture-level-gpu-power-mo/ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesseshttps://computer-arch-dev.hkust.edu.hk/publication/isca2026-icp-exploiting-instruction-correlation/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2026-icp-exploiting-instruction-correlation/IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioninghttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-impart-integration-of-memetic-operation/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-impart-integration-of-memetic-operation/LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Powerhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-leap-a-self-supervised-per-cycle-toggle/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-leap-a-self-supervised-per-cycle-toggle/PF-LLM: Large Language Model Hinted Hardware Prefetchinghttps://computer-arch-dev.hkust.edu.hk/publication/asplos2026-pf-llm-large-language-model-hinted-hard/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asplos2026-pf-llm-large-language-model-hinted-hard/ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Frameworkhttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2026-readypower-a-reliable-interpretable-a/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2026-readypower-a-reliable-interpretable-a/An Architecture-Level CPU Modeling Framework for Power and Other Design Qualitieshttps://computer-arch-dev.hkust.edu.hk/publication/tcad2025-an-architecture-level-cpu-modeling-frame/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-an-architecture-level-cpu-modeling-frame/ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Designhttps://computer-arch-dev.hkust.edu.hk/publication/neurip2025-archpower-dataset-for-architecture-leve/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/neurip2025-archpower-dataset-for-architecture-leve/AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMshttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-assertllm-generating-hardware-verificat/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-assertllm-generating-hardware-verificat/AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decouplinghttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-autopower-automated-few-shot-architectu/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-autopower-automated-few-shot-architectu/FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modelinghttps://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-firepower-towards-a-foundation-with-gen/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-firepower-towards-a-foundation-with-gen/Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiencyhttps://computer-arch-dev.hkust.edu.hk/publication/hpca2025-integrating-prefetcher-selection-with-dy/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/hpca2025-integrating-prefetcher-selection-with-dy/Profile-Guided Temporal Prefetchinghttps://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/isca2025-profile-guided-temporal-prefetching/SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Modelhttps://computer-arch-dev.hkust.edu.hk/publication/iseda2025-specllm-exploring-generation-and-review/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iseda2025-specllm-exploring-generation-and-review/