Jing Wang | HKUST Computer Architecture Grouphttps://computer-arch-dev.hkust.edu.hk/author/jing-wang/Jing WangHugo Blox Builder (https://hugoblox.com)en-usThu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/media/icon_hu_7613a4a452ac7087.pngJing Wanghttps://computer-arch-dev.hkust.edu.hk/author/jing-wang/A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysishttps://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2026-a-self-supervised-and-cross-design-netli/ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioninghttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-compart-community-guided-post-coarsenin/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-compart-community-guided-post-coarsenin/IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioninghttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-impart-integration-of-memetic-operation/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-impart-integration-of-memetic-operation/RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revisionhttps://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-benchmt-dynamic-maintenance-of-rtl/Thu, 01 Jan 2026 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2026-rtl-benchmt-dynamic-maintenance-of-rtl/ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysishttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-atlas-a-self-supervised-and-cross-stage/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-atlas-a-self-supervised-and-cross-stage/CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Designhttps://computer-arch-dev.hkust.edu.hk/publication/iclr2025-circuitfusion-multimodal-circuit-repres/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iclr2025-circuitfusion-multimodal-circuit-repres/GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignmenthttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-geneda-towards-generative-netlist-funct/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-geneda-towards-generative-netlist-funct/HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutionshttps://computer-arch-dev.hkust.edu.hk/publication/iccad2025-hlsdebugger-identification-and-correcti/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/iccad2025-hlsdebugger-identification-and-correcti/RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Techniquehttps://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Modelshttps://computer-arch-dev.hkust.edu.hk/publication/emnlp2025-sync-llm-generation-of-large-scale-synt/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/emnlp2025-sync-llm-generation-of-large-scale-synt/SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuitshttps://computer-arch-dev.hkust.edu.hk/publication/dac2025-syncircuit-automated-generation-of-new/Wed, 01 Jan 2025 00:00:00 +0000https://computer-arch-dev.hkust.edu.hk/publication/dac2025-syncircuit-automated-generation-of-new/