<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Hongce Zhang | HKUST Computer Architecture Group</title><link>https://computer-arch-dev.hkust.edu.hk/author/hongce-zhang/</link><atom:link href="https://computer-arch-dev.hkust.edu.hk/author/hongce-zhang/index.xml" rel="self" type="application/rss+xml"/><description>Hongce Zhang</description><generator>Hugo Blox Builder (https://hugoblox.com)</generator><language>en-us</language><lastBuildDate>Wed, 01 Jan 2025 00:00:00 +0000</lastBuildDate><image><url>https://computer-arch-dev.hkust.edu.hk/media/icon_hu_7613a4a452ac7087.png</url><title>Hongce Zhang</title><link>https://computer-arch-dev.hkust.edu.hk/author/hongce-zhang/</link></image><item><title>A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks</title><link>https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-a-self-supervised-pre-trained-and-cros/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-a-self-supervised-pre-trained-and-cros/</guid><description/></item><item><title>AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs</title><link>https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-assertllm-generating-hardware-verificat/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/asp-da2025-assertllm-generating-hardware-verificat/</guid><description/></item><item><title>NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph</title><link>https://computer-arch-dev.hkust.edu.hk/publication/dac2025-nettag-a-multimodal-rtl-and-layout-alig/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/dac2025-nettag-a-multimodal-rtl-and-layout-alig/</guid><description/></item><item><title>RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique</title><link>https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-rtlcoder-fully-open-source-and-efficien/</guid><description/></item><item><title>Transferable Pre-Synthesis PPA Estimation for RTL Designs with Data Augmentation Techniques</title><link>https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-transferable-pre-synthesis-ppa-estimatio/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/tcad2025-transferable-pre-synthesis-ppa-estimatio/</guid><description/></item></channel></rss>