<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>C. Ma | HKUST Computer Architecture Group</title><link>https://computer-arch-dev.hkust.edu.hk/author/c.-ma/</link><atom:link href="https://computer-arch-dev.hkust.edu.hk/author/c.-ma/index.xml" rel="self" type="application/rss+xml"/><description>C. Ma</description><generator>Hugo Blox Builder (https://hugoblox.com)</generator><language>en-us</language><lastBuildDate>Wed, 01 Jan 2025 00:00:00 +0000</lastBuildDate><image><url>https://computer-arch-dev.hkust.edu.hk/media/icon_hu_7613a4a452ac7087.png</url><title>C. Ma</title><link>https://computer-arch-dev.hkust.edu.hk/author/c.-ma/</link></image><item><title>DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator</title><link>https://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-draco-co-design-for-dsp-efficient-rigid/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-draco-co-design-for-dsp-efficient-rigid/</guid><description/></item><item><title>FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration</title><link>https://computer-arch-dev.hkust.edu.hk/publication/icpp2025-flex-leveraging-fpga-cpu-synergy-for-mi/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/icpp2025-flex-leveraging-fpga-cpu-synergy-for-mi/</guid><description/></item><item><title>HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantization</title><link>https://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-hero-hardware-efficient-rl-based-optimi/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://computer-arch-dev.hkust.edu.hk/publication/arxiv2025-hero-hardware-efficient-rl-based-optimi/</guid><description/></item></channel></rss>